题解 | #输入序列不连续的序列检测#

//又是打一拍{ram[2:0],data}==4'b0110
`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg [3:0]ram;
always@(posedge clk or negedge rst_n )begin
if(!rst_n)
ram<=0;
else if(data_valid)
ram<={ram[2:0],data};
else if (!data_valid)
ram<=0;
else
ram <=0;
end

  always@(posedge clk or negedge rst_n )begin
	if(!rst_n)
match<=0;
else if({ram[2:0],data}==4'b0110)
match<=1;
else
match<=0;
  end
endmodule