题解 | #不重叠序列检测#

注意

1、要增加一个FAIL状态；

2、增加一个基数cnt；

3、注意FAIL状态的next_state；

4、注意match和not_match的赋值条件

有一点想知道：下面逻辑部分，我注释掉的部分需要添加吗？我看都能通过。不太清楚这里加和不加的影响，希望大牛能给解答下。

	always@(*)begin
		// if(~rst_n)
		// 	cur_state = IDLE;
		// else
		case(cur_state)
			IDLE: next_state = data? FAIL:S1;
			S1:	  next_state = data? S2:FAIL;

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	
	parameter IDLE=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, FAIL=7;
	reg [2:0] cur_state, next_state;
	reg [2:0] cnt;

	always@(posedge clk or negedge rst_n)begin
		if(~rst_n)
			cnt <= 0;
		else
			cnt <= cnt==6? 1:cnt+1;
	end

	always@(posedge clk or negedge rst_n)begin
		if(~rst_n)
			cur_state <= IDLE;
		else
			cur_state <= next_state;
	end

	always@(*)begin
		// if(~rst_n)
		// 	cur_state = IDLE;
		// else
		case(cur_state)
			IDLE: next_state = data? FAIL:S1;
			S1:	  next_state = data? S2:FAIL;
			S2:   next_state = data? S3:FAIL;
			S3:   next_state = data? S4:FAIL;
			S4:   next_state = data? FAIL:S5;
			S5:   next_state = data? FAIL:S6;
			S6:   next_state = data? FAIL:S1;
			FAIL: next_state = cnt==6&&data==0? S1:FAIL;

			default: next_state = IDLE;

		endcase
	end

	always@(*)begin
		if(~rst_n)begin
			match = 0;
			not_match =0;
		end
		else begin
			match = cnt==6&&cur_state==S6;
			not_match = cnt==6&&cur_state==FAIL;
		end
	end

endmodule