题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

//多比特的慢时钟域到快时钟域

//1、data_in在慢时钟域打一拍寄存 (D触发器)
reg		[3:0] data_in_b;
always@(posedge clk_a or negedge arstn)
begin
	if(~arstn)
		data_in_b	<=	0;
	else
		data_in_b	<=	data_in;
end
//2、data_en在慢时钟域打一拍寄存 (D触发器)
reg		data_en_d0;
always@(posedge clk_a or negedge arstn)
begin
	if(~arstn)
		data_en_d0	<=	0;
	else
		data_en_d0	<=	data_en;
end

//3、在快时钟域下，把data_en_d0打两拍
reg		data_en_d1;
reg		data_en_d2;
always@(posedge clk_b or negedge brstn)
begin
	if(~brstn)
	begin
		data_en_d1	<=	0;
		data_en_d2	<=	0;
	end
	else begin
		data_en_d1	<=	data_en_d0;
		data_en_d2	<=	data_en_d1;
	end
end
//4、得到data_en_d2作为数据选择器的输入，传给dataout
always@(posedge clk_b or negedge brstn)
begin
	if(~brstn)
		dataout	<=	0;
	else
		dataout	<=	data_en_d2 ? data_in_b : dataout;
end
endmodule