题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

	wire data_tmp1;
	reg data_tmp2;

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			data_out <= 1'b0;
		end
		else begin
			data_out <= data_tmp1;
		end
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			data_tmp2 <= 1'b0; 
		end
		else begin
			data_tmp2 <= data_in;
		end
	end

	assign data_tmp1 = data_in & ~data_tmp2;

endmodule