题解 | #根据状态转移表实现时序电路#
根据状态转移表实现时序电路
https://www.nowcoder.com/practice/455c911bee0741bf8544a75d958425f7?tpId=301&tqId=5000590&ru=/exam/oj&qru=/ta/verilog-start/question-ranking&sourceUrl=%2Fexam%2Foj%3Fpage%3D1%26tab%3DVerilog%25E7%25AF%2587%26topicId%3D301
`timescale 1ns/1ns
module seq_circuit(
input A ,
input clk ,
input rst_n,
output wire Y
);
parameter ST0 = 2'b00;
parameter ST1 = 2'b01;
parameter ST2 = 2'b10;
parameter ST3 = 2'b11;
reg [1:0] state_c;
reg [1:0] state_n;
reg r_y;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
state_c <= ST0;
end
else begin
state_c <= state_n;
end
end
always@(*)begin
case(state_c)
ST0:begin
if(A==1'b0)begin
state_n <= ST1;
end
else begin
state_n <= ST3;
end
end
ST1:begin
if(A==1'b0)begin
state_n <= ST2;
end
else begin
state_n <= ST0;
end
end
ST2:begin
if(A==1'b0)begin
state_n <= ST3;
end
else begin
state_n <= ST1;
end
end
ST3:begin
if(A==1'b0)begin
state_n <= ST0;
end
else begin
state_n <= ST2;
end
end
endcase
end
always@(*)begin
case(state_c)
ST0:begin
r_y <= 1'b0;
end
ST1:begin
r_y <= 1'b0;
end
ST2:begin
r_y <= 1'b0;
end
ST3:begin
r_y <= 1'b1;
end
endcase
end
assign Y = r_y;
endmodule
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