题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);

reg data_fast_out;
always@(posedge clk_fast or negedge rst_n) begin
	if(!rst_n) begin
		data_fast_out <= 0;
	end
	else begin
		data_fast_out <= data_in? ~data_fast_out : data_fast_out;
	end
end
reg data_tmp1,data_tmp2,data_tmp3;
always@(posedge clk_slow or negedge rst_n) begin
	if(!rst_n) begin
		data_tmp1 <= 0;
		data_tmp2 <= 0;
		data_tmp3 <= 0;
	end
	else begin
		data_tmp1 <= data_fast_out;
		data_tmp2 <= data_tmp1;
		data_tmp3 <= data_tmp2;
	end
end
assign dataout = data_tmp3 ^ data_tmp2;

endmodule