题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg [1:0] cnt;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt = 0;
	end
	else if (valid_a && ready_a)
		cnt <= (cnt==2'd3)? 0 : cnt + 1;
	else
		cnt <= cnt;
end
//data_out
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_out <= 0;
	end
	else if(ready_a && valid_a)
		data_out <= (cnt==2'd0) ? data_in : (data_out + data_in);
	else
		data_out <= data_out;
end
//valid_b
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		valid_b <= 0;
	end	
	else if(cnt==2'd3 && valid_a && ready_a)
		valid_b <= 1; 
	else if(ready_b && valid_b)
		valid_b <= 0;
end
//ready_a
assign ready_a = !valid_b | ready_b;
endmodule