题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
localparam idle = 4'b0000,
		   s_0p5 = 4'b0001,
		   s_1p0 = 4'b0010,
		   s_1p5 = 4'b0011,
		   s_2p0 = 4'b0100,
		   s_2p5 = 4'b0101,
		   s_3p0 = 4'b0110,
		   over = 4'b0111;

reg [3:0] state, nstate, nstate_reg;

always @(posedge clk or negedge rst) begin
	if(!rst)
		state <= idle;
	else
		state <= nstate_reg;
end

always @(*)(1444584) begin
	if(!rst) 
		nstate = idle;
	else	
		case(state)
			idle: nstate = d1 ? s_0p5 : (d2 ? s_1p0 : idle);
			s_0p5: nstate = d1 ? s_1p0 : (d2 ? s_1p5 : s_0p5);
			s_1p0: nstate = d1 ? s_1p5 : (d2 ? s_2p0 : s_1p0);
			s_1p5: nstate = !sel ? idle : (d1 ? s_2p0 : (d2 ? s_2p5 : s_1p5));
			s_2p0: nstate = !sel ? idle : (d1 ? s_2p5 : (d2 ? s_3p0 : s_2p0));
			s_2p5: nstate = idle;
			s_3p0: nstate = idle;
			default: nstate = idle;
		endcase
end

always @(negedge clk) begin
	nstate_reg <= nstate;
end

always @(posedge clk or negedge rst) begin
	if(!rst) 
		{out1, out2, out3} <= 3'b000;
	else if(nstate_reg == s_1p5 && !sel) 
		{out1, out2, out3} <= 3'b100;
	else if(nstate_reg == s_2p0 && !sel)
		{out1, out2, out3} <= 3'b101;
	else if(nstate_reg == s_2p5 && sel)
		{out1, out2, out3} <= 3'b010;
	else if(nstate_reg == s_3p0 && sel)
		{out1, out2, out3} <= 3'b011;
	else
		{out1, out2, out3} <= 3'b000;
end

//*************code***********//
endmodule