题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

    wire S_half1,C_half1;
    wire S_half2,C_half2;

    add_half inst0(
        .A          (A )  ,
        .B          (B )  ,
 
        .S          (S_half1 )  ,
        .C          (C_half1 )  
);

    add_half inst1(
        .A          (S_half1 )  ,
        .B          (Ci )  ,
 
        .S          (S_half2 )  ,
        .C          (C_half2 )  
);

assign S = S_half2;
assign Co = C_half2 | C_half1;
   


endmodule