题解 | #超前进位加法器#

`timescale 1ns/1ns

module huawei8//四位超前进位加法器
(
	input wire [3:0]A,
	input wire [3:0]B,
	output wire [4:0]OUT
);

//*************code***********//
	wire [3:0] G,P,F;
	wire [4:1] C;

	Add1 inst0(
		.a 		(A[0]),
		.b 		(B[0]),
		.C_in 	(1'b0),
		.f 		(F[0]),
		.g 		(G[0]),
		.p 		(P[0])
	);

	genvar i;
	generate 
		for(i=1;i<4;i=i+1) begin:Add1_inst
			Add1 inst(
				.a 		(A[i]),
				.b 		(B[i]),
				.C_in 	(C[i]),
				.f 		(F[i]),
				.g 		(G[i]),
				.p 		(P[i])
			);
		end
	endgenerate

	 CLA_4 inst_cal(
		.P			(P),
		.G			(G),
		.C_in		(1'b0),
		.Ci			(C),
		.Gm			(),
		.Pm			()
	);

	assign OUT = {C[4],F};



//*************code***********//
endmodule



//////////////下面是两个子模块////////

module Add1
(
		input a,
		input b,
		input C_in,
		output f,
		output g,
		output p
		);

	assign g = a & b;
	assign p = a | b;
	assign f = a ^ b ^ C_in; //sum

endmodule



module CLA_4(
		input [3:0]P,
		input [3:0]G,
		input C_in,
		output [4:1]Ci,
		output Gm,
		output Pm
	);

	assign Ci[1] = G[0] | P[0] & C_in;
	assign Ci[2] = G[1] | P[1] & (G[0] | P[0] & C_in);
	assign Ci[3] = G[2] | P[2] & (G[1] | P[1] & (G[0] | P[0] & C_in));
	assign Ci[4] = G[3] | P[3] & (G[2] | P[2] & (G[1] | P[1] & (G[0] | P[0] & C_in)));

	assign Gm = G[3] | (P[3]&G[2]) | (P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]);
	assign Pm = P[3]&P[2]&P[1]&P[0];
	
endmodule