题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

	reg [5:0] data_r;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_r <= 6'b001011;
		else
			data_r <= {data_r[4:0],data_r[5]};
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data <= 1'b0;
		else
			data <= data_r[5];
	end
endmodule