题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);

	reg [3:0] num;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			num <= 'd0;
		else if(set)
			num <= set_num;
		else if(num == 'd15)
			num <= 'd0;
		else
			num <= num + 1'b1;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			number <= 'd0;
		else
			number <= num;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			zero <= 1'b0;
		else if(num == 'd0)
			zero = 1'b1;
		else	
			zero = 1'b0;
	end
endmodule