题解 | #简易秒表#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			second <= 6'd0;
		else if(second == 'd60)
			second <= 6'd1;
		else if(minute != 'd60)
			second <= second + 1'b1;
		else
			second <= second;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			minute <= 'd0;
		else if(second == 'd60)
			minute <= minute + 1'b1;
		else if(minute == 'd60)
			minute <= minute;
		else
			minute <= minute;
	end

	
endmodule