题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
    reg [2:0] cnt;
    reg clk_out7_r1,clk_out7_r2;

    always @(posedge clk_in or negedge rst) begin
        if(rst == 1'b0)
            cnt <= 3'd0;
        else if(cnt == 3'd6)
            cnt <= 3'd0;
        else
            cnt <= cnt + 1'b1;
    end

    always @(posedge clk_in or negedge rst) begin
        if(rst == 1'b0)
            clk_out7_r1 <= 1'b0;
        else if(cnt == 3'd3)
            clk_out7_r1 <= 1'b1;
        else if(cnt == 3'd6)
            clk_out7_r1 <= 1'b0;
        else
            clk_out7_r1 <= clk_out7_r1;
    end

    always @(negedge clk_in or negedge rst)begin
        if(rst == 1'b0)
            clk_out7_r2 <= 1'b0;
        else if(cnt == 3'd3)
            clk_out7_r2 <= 1'b1;
        else if(cnt == 3'd6)
            clk_out7_r2 <= 1'b0;
        else
            clk_out7_r2 <= clk_out7_r2;
    end

    assign clk_out7 = clk_out7_r1 || clk_out7_r2;
   

//*************code***********//
endmodule