题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
	reg [2:0] cur_st,nxt_st;
	parameter zero = 3'd0,
			  half = 3'd1,
			  one = 3'd2,
			  onehalf = 3'd3,
			  two = 3'd4,
			  twohalf = 3'd5,
			  three = 3'd6;

	always @(posedge clk or negedge rst)begin
		if(rst == 1'b0)
			cur_st <= 3'd0;
		else
			cur_st <= nxt_st;
	end

	always @(*)(1444584) begin
		if(sel)begin
		case(cur_st)
			zero:begin
					if(d1)
						nxt_st = half;
					else if(d2)
						nxt_st = one;
					else
						nxt_st = nxt_st;
			end
			half:begin
					if(d1)
						nxt_st = one;
					else if(d2)
						nxt_st = onehalf;
					else
						nxt_st = nxt_st;
			end
			one:begin
					if(d1)
						nxt_st = onehalf;
					else if(d2)
						nxt_st = two;
					else
						nxt_st = nxt_st;
			end
			onehalf: begin
						if(d1)
							nxt_st = two;
						else if(d2)
							nxt_st = twohalf;
						else
							nxt_st = nxt_st;
			end
			two: begin
					if(d1)
						nxt_st = twohalf;
					else if(d2)
						nxt_st = three;
					else	
						nxt_st = nxt_st;
			end
			twohalf: nxt_st = zero;
			three: nxt_st = zero;
			default: nxt_st = zero;
		endcase
		end
		else begin
			case(cur_st)
			zero:begin
					if(d1)
						nxt_st = half;
					else if(d2)
						nxt_st = one;
					else
						nxt_st = nxt_st;
			end
			half:begin
					if(d1)
						nxt_st = one;
					else if(d2)
						nxt_st = onehalf;
					else
						nxt_st = nxt_st;
			end
			one:begin
					if(d1)
						nxt_st = onehalf;
					else if(d2)
						nxt_st = two;
					else
						nxt_st = nxt_st;
			end
			onehalf: nxt_st = zero;
			two: nxt_st = zero;
			default: nxt_st = zero;
		endcase
		end
	end

	always @(*)(1444584) begin
		if(sel)begin
		case(cur_st)
			twohalf: begin out2 = 1'b1; out3 = 1'b0; end
			three: begin out2 = 1'b1; out3 = 1'b1; end
			default: begin out1 = 1'b0;out2 = 1'b0; out3 = 1'b0; end
		endcase
		end
		else begin
		case(cur_st)
			onehalf: begin out1 = 1'b1; out3 = 1'b0; end
			two: begin out1 = 1'b1; out3 = 1'b1; end
			default: begin out1 = 1'b0; out2 = 1'b0;out3 = 1'b0; end
		endcase
		end
	end

//*************code***********/
endmodule