题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
	reg [2:0] cur_st,nxt_st;

	parameter IDLE = 3'd0,
			  s0   = 3'd1,
			  s1   = 3'd2,
			  s2   = 3'd3,
			  s3   = 3'd4,
			  s4   = 3'd5;

	always @(posedge clk or negedge rst) begin
		if(rst == 1'b0)
			cur_st <= IDLE;
		else
			cur_st <= nxt_st;
	end
 
	always @(*)(1444584) begin
		case(cur_st)
			IDLE: begin
					if(data == 1'b1)
						nxt_st = s0;
					else
						nxt_st = IDLE;
			end
			s0:begin
					if(data == 1'b0)
						nxt_st = s1;
					else
						nxt_st = s0;
			end
			s1:begin
					if(data == 1'b1)
						nxt_st = s2;
					else 
						nxt_st = IDLE;
			end
			s2:begin
					if(data == 1'b1)
						nxt_st = s3;
					else
						nxt_st = s1;
			end
			s3:begin
					if(data == 1'b1)
						nxt_st = s4;
					else
						nxt_st = s1; 
			end
			s4:begin
					if(data == 1'b1)
						nxt_st = s0;
					else
						nxt_st = IDLE;
			end
			default: nxt_st = IDLE;
		endcase
		
	end

	//always @(posedge clk or negedge rst)begin
	//	if(rst == 1'b0)
	//		flag <= 1'b0;
	//	else if(cur_st == s4)
	//		flag <= 1'b1;
	//	else
	//		flag <= 1'b0;
	//end

	always @(*)begin
		if(cur_st == s4)
			flag = 1'b1;
		else
			flag = 1'b0;
	end

//*************code***********//
endmodule

咱就是说，这个flag,如果写成时序逻辑，用vivado仿真波形和题目给的一致，但是不通过，改成组合逻辑，波形有一拍之差，但是通过。。。