题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b 
);

	reg [2:0] data_cnt;
	reg [5:0] data_b_r;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_cnt <= 3'd0;
		else if(data_cnt == 3'd5)
			data_cnt <= 3'd0;
		else if(valid_a && ready_a)
			data_cnt <= data_cnt + 1'b1;
		else
			data_cnt <= data_cnt;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_b_r <= 6'd0;
		else if(valid_a && ready_a)
			data_b_r <= {data_a,data_b_r[5:1]};
		else
			data_b_r <= data_b_r;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			valid_b <= 1'b0;
		else if(data_cnt == 3'd5)
			valid_b <= 1'b1;
		else
			valid_b <= 1'b0;
	end

	//always @(*)(1444584) begin
	//	if(valid_b == 1'b1)
	//		data_b = data_b_r;
	//	else
	//		data_b = data_b;
	//end

	always @(posedge clk or negedge rst_n)begin
		if(rst_n == 1'b0)
			data_b <= 6'd0;
		else if(data_cnt == 3'd5)
			data_b <= {data_a,data_b_r[5:1]};
		else
			data_b <= data_b;
	end

	
	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			ready_a <= 1'b0;
		else 
			ready_a <= 1'b1;
	end
	

	
endmodule