题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);

	reg [4:0] cnt;
	reg flag;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			cnt <= 5'd0;
		else if(cnt == 5'd19)
			cnt <= 5'd0;
		else
			cnt <= cnt + 1'b1;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)begin
			wave <= 5'd0;
			flag <= 1'b0;
		end
		else begin
			case(wave_choise)
			2'd0: begin
					if(cnt == 5'd9)
						wave <= 5'd20;
					else if(cnt == 5'd19)
						wave <= 5'd0;
					else
						wave <= wave;
			end
			2'd1: begin
					if(wave == 5'd20)
						wave <= 5'd0;
					else
						wave <= wave + 1'b1;					 
			end
			2'd2: begin
					if(wave == 5'd0)begin
						wave <= 5'd1;
						flag <= 1'b1;
					end
					else if(wave == 5'd20)begin
						wave <= 5'd19;
						flag <= 1'd0;
					end
					else
						wave <= flag ? wave + 1'b1 : wave - 1'b1;
			end
			default: wave <= 5'd0;
			endcase
		end		
	end

	 
endmodule

这个题做的真是恶心哦，搞了好久。大家用vivado仿真的时候，选模拟时选择 hold,因为默认是linear。这样才能出最终波形。祝顺利！