题解 | #编写乘法器求解算法表达式#

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output wire  [8:0] c
	);
wire [7:0] a8,a4;
wire [7:0] b4,b1;
wire [8:0] c_wire;

reg [8:0] c1,c2;



assign a8 = a<<3;
assign a4 = a<<2;
assign b4 = b<<2;


assign  c_wire= (a8+a4+b4+b);  
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
	c1<='b0;
	c2<='b0;
end else begin
	c1<=c_wire;
	c2<=c1;
end
assign c=c2;

endmodule