题解 | #不重叠序列检测#

自己仿真没啥问题，但是牛客网的提交总是通过不了。有大佬不怕麻烦的话，帮我看看提出问题。

module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

//*************code***********//
parameter [2:0]	s0 = 3'b000,
				s1 = 3'b001,		
				s2 = 3'b010,
				s3 = 3'b011,
				s4 = 3'b100,	
				s5 = 3'b101,
				s6 = 3'b110,
				s7 = 3'b111;
						
reg [2:0] curr_state;
reg [2:0] next_state;
reg [2:0] cnt;

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		cnt <= 3'd0;
	else if(cnt == 3'd6)
		cnt <= 3'd1;
	else	
		cnt <= cnt + 1'b1;
end


//第一段 状态转移
always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		curr_state <= s0;
	else if(cnt == 3'd6)
		curr_state <= s1;		
	else
		curr_state <= next_state;
	end

//第二段 转移状况
always @(*)begin

	case(curr_state)
		s0:	begin next_state = s1;end	
		s1:	begin
				if(data==0) 	next_state = s2;
				else 			next_state = s1;	
			end
		s2:	begin
				if(data==1) 	next_state = s3;
				else 			next_state = s1;	
			end
		s3:	begin
				if(data==1) 	next_state = s4;
				else 			next_state = s1;	
			end
		s4:	begin
				if(data==1) 	next_state = s5;
				else 			next_state = s1;	
			end
		s5:	begin
				if(data==0) 	next_state = s6;
				else 			next_state = s1;	
			end
		s6:	begin
				if(data==0) 	next_state = s7;
				else 			next_state = s1;	
			end
		s7:	begin next_state = s1;end			
		default: begin next_state = s1;end
	endcase	   
end
	
/********* 第三段 状态输出 moore FSM ************/

//标志信号
always @(posedge clk or negedge rst_n)begin 
	if(!rst_n)begin
		match <= 1'b0;	
		not_match <= 1'b0;	
	end
	else if(next_state == s7 && cnt == 3'd6)begin
		match <= 1'b1;	
		not_match <= 1'b0;	
	end
	else if(next_state != s7 && cnt == 3'd6)begin
		match <= 1'b0;	
		not_match <= 1'b1;	
	end	
	else begin
		match <= 1'b0;
		not_match <= 1'b0;			
	end
end 

//*************code***********// 
endmodule