题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	reg a_r;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			a_r <= 1'b0;
		else 
			a_r <= a;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			rise <= 1'b0;
		else if(a == 1'b1 && a_r == 1'b0)
			rise <= 1'b1;
		else if(rise == 1'b1)
			rise <= 1'b0;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			down <= 1'b0;
		else if(a == 1'b0 && a_r == 1'b1)
			down <= 1'b1;
		else if(down == 1'b1)
			down <= 1'b0;
	end
endmodule