题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
    
    
    reg    [1:0]    data_in_cnt;
    reg    [11:0]   data_out_temp;
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            data_in_cnt <= 2'b0;
        else if(valid_in)
            begin
                if(data_in_cnt == 2'b10)
                    data_in_cnt <= 2'b0;
                else
                    data_in_cnt <= data_in_cnt + 1'b1;
            end
        else
            data_in_cnt <= data_in_cnt;
    end
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            data_out_temp <= 12'b0;
        else if(valid_in)
            data_out_temp <= {data_out_temp[3:0] , data_in};
        else
            data_out_temp <= data_out_temp;
    end
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            begin
                data_out <= 12'b0;
                valid_out <= 1'b0;
            end
        else if(valid_in)        //这里和之前的有区别，必须要加上数据有效，因为其不加上下面的有效位和数据位还是与当前数据进行计算导致输出出错
            begin
                case(data_in_cnt)
                    2'b00    :    begin
                            data_out <= data_out;
                            valid_out <= 1'b0;
                        end
                    2'b01    :    begin
                            data_out <= {data_out_temp[7:0] , data_in[7:4]};    //这里的截取和temp的截取不一致，所以必须加上valid判断
                            valid_out <= 1'b1;
                        end
                    2'b10    :    begin
                            data_out <= {data_out_temp[3:0] , data_in};    //不加上面的valid判断这里就会还继续运行，就会报错，因为这里和前面的所截取的不一致，以及temp也不一致，所以会导致出错
                            valid_out <= 1'b1;
                        end
                    default  :    begin
                            data_out <= data_out;
                            valid_out <= 1'b0;
                        end
                endcase
            end
        else
            begin
                data_out <= data_out;
                valid_out <= 1'b0;
            end
    end
    
endmodule