题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output    reg         Y   
);
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;//定义5个状态，这里直接定义，使用独热码会更好
reg [2:0] state,nstate;//定义现在状态和下一状态
always@(posedge clk or negedge rst_n)//描述现态向次态转移
begin
if(!rst_n)
state<=s0;
else
state<=nstate;
end

always @(*)//检测序列输入
begin
if(!rst_n)
nstate<=s0;
else
begin
case(state)
s0:begin
if(din==1)
nstate<=s1;
else
nstate<=s0;
end
s1:begin
if(din==1)
nstate<=s2;
else
nstate<=s0;
end
s2:begin
if(din==0)
nstate<=s3;
else
nstate<=s2;
end
s3:begin
if(din==1)
nstate<=s4;
else
nstate<=s0;
end
s4:begin
if(din==1)
nstate<=s1;
else
nstate<=s0;
end
default:state<=s0;
endcase
end
end

begin
if(!rst_n)
Y<=0;
else
begin
if(state==s4)
Y<=1;
else
Y<=0;
end
end
endmodule