题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//

reg    [3:0]    ram_reg    [127:0];
reg    [3:0]    r_data_reg;

genvar    i;
generate
    for(i=0;i<128;i=i+1)
        always@(posedge clk or negedge rst)begin 
            if(!rst)begin 
                ram_reg[i] <= 0; 
            end
            else    if(enb)begin 
                ram_reg[addr] <= w_data; 
            end
            else    begin 
                ram_reg[addr] <= ram_reg[addr]; 
            end
        end
endgenerate

always@(*)begin 
    if(!rst)begin 
       r_data_reg <= 0; 
    end
    else    if(enb)begin 
        r_data_reg <=  r_data_reg;
    end
    else    begin 
        r_data_reg <= ram_reg[addr]; 
    end
end

assign r_data = r_data_reg;


//*************code***********//
endmodule