题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
    
   reg    [3:0]    rom_data    [7:0];

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
        rom_data[0] <= 4'b0000;
        rom_data[1] <= 4'b0010; 
        rom_data[2] <= 4'b0100; 
        rom_data[3] <= 4'b0110; 
        rom_data[4] <= 4'b1000; 
        rom_data[5] <= 4'b1010; 
        rom_data[6] <= 4'b1100; 
        rom_data[7] <= 4'b1110; 
    end
    else    begin 
        rom_data[0] <= 4'b0000;
        rom_data[1] <= 4'b0010; 
        rom_data[2] <= 4'b0100; 
        rom_data[3] <= 4'b0110; 
        rom_data[4] <= 4'b1000; 
        rom_data[5] <= 4'b1010; 
        rom_data[6] <= 4'b1100; 
        rom_data[7] <= 4'b1110;   
    end
end

assign data = rom_data[addr];

endmodule