题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
    parameter   S0 = 5'b00001,
                S1 = 5'b00010,
                S2 = 5'b00100,
                S3 = 5'b01000,
                S4 = 5'b10000;

reg    [4:0]    st_cur;
reg    [4:0]    st_next;

always@(posedge clk or negedge rst)begin 
    if(!rst)begin 
       st_cur <= 5'd0;
    end
    else    begin 
       st_cur <= st_next; 
    end
end

always@(*)begin 
    if(!rst)begin 
       st_next = 5'd0;
        flag = 1'b0;
    end
    else    begin 
        case(st_cur)
            S0 : begin 
                st_next = data? S1:S0;
                flag = 1'b0;
            end
            S1 : begin 
                st_next = data? S2:S1;
                flag = 1'b0;
            end
            S2 : begin 
                st_next = data? S3:S2;
                flag = 1'b0;
            end
            S3 : begin 
                st_next = data? S4:S3;
                flag = 1'b0;
            end
            S4 : begin 
                st_next = data? S1:S0;
                flag = 1'b1;
            end
            default : begin 
                st_next = S0;
                flag = 1'b0;
            end        
        endcase
    end
end

//*************code***********//
endmodule