题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
    parameter   s0 = 7'b0000_001,//
                s1 = 7'b0000_010,//0.5
                s2 = 7'b0000_100,//1
                s3 = 7'b0001_000,//1.5
                s4 = 7'b0010_000,//2
                s5 = 7'b0100_000,//2.5
                s6 = 7'b1000_000;//3
    
reg    [6:0]    st_cur;
reg    [6:0]    st_next;

wire    [1:0]    pi_money;

assign pi_money = {d2,d1};

always@(posedge clk or negedge rst)begin 
    if(!rst)begin 
       st_cur <= 7'b0; 
    end
    else    begin 
       st_cur <= st_next; 
    end
end

always@(*)begin 
    case(st_cur)
        s0 : case(pi_money)
            2'b01 : st_next <= s1;
            2'b10 : st_next <= s2;
            default : st_next <= st_next;     
        endcase
        s1 : case(pi_money)
            2'b01 : st_next <= s2;
            2'b10 : st_next <= s3;
            default : st_next <= st_next;
        endcase
        s2 : case(pi_money)
            2'b01 : st_next <= s3;
            2'b10 : st_next <= s4;
            default : st_next <= st_next;
        endcase
        s3 : if(!sel)begin 
                st_next <= s0;
            end
            else    begin 
                case(pi_money)
                    2'b01 : st_next <= s4;
                    2'b10 : st_next <= s5;
                    default : st_next <= st_next;
                endcase
            end
        s4 : if(!sel)begin 
                st_next <= s0;
            end
            else    begin 
                case(pi_money)
                    2'b01 : st_next <= s5;
                    2'b10 : st_next <= s6;
                    default : st_next <= st_next;
                endcase
            end
        s5 : st_next <= s0;
        s6 : st_next <= s0;
        default : st_next <= s0;  
    endcase
end

always@(posedge clk or negedge rst)begin 
    if(!rst)begin
        out1 <= 1'b0;
        out2 <= 1'b0;
        out3 <= 1'b0;
    end
    else    case(st_next)
        s3 : if(!sel)begin 
                out1 <= 1'b1;
                out2 <= 1'b0;
                out3 <= 1'b0;
        end
        else    begin 
                out1 <= 1'b0;
                out2 <= 1'b0;
                out3 <= 1'b0; 
        end
        s4 : if(!sel)begin 
                out1 <= 1'b1;
                out2 <= 1'b0;
                out3 <= 1'b1;
        end
        else    begin 
                out1 <= 1'b0;
                out2 <= 1'b0;
                out3 <= 1'b0;
        end
        s5 : if(!sel)begin 
                out1 <= 1'b1;
                out2 <= 1'b0;
                out3 <= 1'b1;
        end
        else    begin 
                out1 <= 1'b0;
                out2 <= 1'b1;
                out3 <= 1'b0; 
        end
        s6 : if(!sel)begin 
                out1 <= 1'b1;
                out2 <= 1'b0;
                out3 <= 1'b1;
        end
        else    begin 
                out1 <= 1'b0;
                out2 <= 1'b1;
                out3 <= 1'b1;
        end
        default : begin 
                 out1 <= 1'b0;
                 out2 <= 1'b0;
                 out3 <= 1'b0; 
        end  
    endcase
end
//*************code***********//
endmodule