题解 | #状态机-重叠序列检测#

用三段式状态机编写

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//machine state decode
    parameter    IDLE    =    3'd0,
                 s_1     =    3'd1,
                 s_10    =    3'd2,
                 s_101   =    3'd3,
                 s_1011  =    3'd4;
//machine variable    
    reg    [2:0]    st_next;
    reg    [2:0]    st_cur ;
//(1) state transfer    
    always@(posedge clk or negedge rst)begin 
        if(!rst)begin 
           st_cur <= 3'd0; 
        end
        else    begin 
           st_cur <= st_next; 
        end
    end
//(2) state switch, using block assignment for combination-logic   
    always@(*)begin 
        case(st_cur)
            IDLE : case(data)
                1'b0 : st_next <= IDLE;
                1'b1 : st_next <= s_1;
                default : st_next <= IDLE;
            endcase
            s_1 : case(data)
                1'b0 : st_next <= s_10;
                1'b1 : st_next <= s_1;
                default : st_next <= s_1;
            endcase
            s_10 : case(data)
                1'b0 : st_next <= IDLE;
                1'b1 : st_next <= s_101;
                default : st_next <= s_10;
            endcase
            s_101 : case(data)
                1'b0 : st_next <= s_10;
                1'b1 : st_next <= s_1011;
                default : st_next <= s_101;
            endcase
            s_1011 : case(data)
                1'b0 : st_next <= s_10;
                1'b1 : st_next <= s_1;
                default : st_next <= s_1011;
            endcase
            default : st_next <= IDLE; 
        endcase
    end
//(3) output logic, using non-block assignment    
    always@(posedge clk or negedge rst)begin 
        if(!rst)begin 
            flag <= 1'b0;
        end
        else    if(st_cur == s_1011)begin 
            flag <= 1'b1;
        end
        else    begin 
           flag <= 1'b0; 
        end
    end
//*************code***********//
endmodule