题解 | #多bit MUX同步器#

跨时钟域传输，电路图如图所示：

完整代码：

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
    reg[3:0]data_in1;
    reg data_ena1,data_enb1,data_enb2;
    always@(posedge clk_a or negedge arstn)begin
        if(!arstn)begin
            data_in1 <= 0;
            data_ena1 <= 0;
        end
        else begin
            data_in1 <= data_in;
            data_ena1 <= data_en;
        end
    end
    
    always@(posedge clk_b or negedge brstn)begin
        if(!brstn)begin
            data_enb1 <= 0;
            data_enb2 <= 0;
        end
        else begin
            data_enb1 <= data_ena1;
            data_enb2 <= data_enb1;
        end
    end
    
    always@(posedge clk_b or negedge brstn)begin
        if(~brstn)
            dataout <= 0;
        else 
            dataout <= data_enb2? data_in1: dataout;
    end
                   
endmodule