题解 | #边沿检测#
边沿检测
http://www.nowcoder.com/practice/fed4247d5ef64ac68c20283ebace11f4
麻烦有看到的大佬给解答下，为啥红色的分支部分不添加，编译就无法通过，原本的想法是直接这么写
always @ (*)
begin
if(!rst_n)
begin
rise = 1'b0;
down = 1'b0;
end
else
begin
rise = (a_t0 && (~a_t1)) ? 1'b1 : 1'b0;
down = ((~a_t0) && a_t1) ? 1'b1 : 1'b0;
end
end
`timescale 1ns/1ns
module edge_detect(
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
//------------reg define----------//
reg a_t0;
reg a_t1;
//-----------wire define-----------//
//***********************************//
// Main code
//***********************************//
// assign rise = a_t0 && (~a_t1);
// assign down = (~a_t0) && a_t1;
//边沿检测:双沿检测
always @ (posedge clk,negedge rst_n)
begin
if(!rst_n)
begin
a_t0 <= 1'b0;
a_t1 <= 1'b0;
end
else
begin
a_t0 <= a;
a_t1 <= a_t0;
end
end
//output
always @ (*)
begin
if(!rst_n)
begin
rise = 1'b0;
down = 1'b0;
end
else if((a_t0 && (~a_t1)) || ((~a_t0) && a_t1))
begin
rise = (a_t0 && (~a_t1)) ? 1'b1 : 1'b0;
down = ((~a_t0) && a_t1) ? 1'b1 : 1'b0;
end
else
begin
rise = 1'b0; //这段代码不加就通过不了呗
down = 1'b0;
end
end
endmodule
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