题解 | #多bit MUX同步器#

用计数器来做 当data_en=1时开始计数，当计数3次时，将输入数据data_in在clk_a时钟域内传递给临时存储器data，然后再clk_b的时钟域内将临时存储器data的值传递给输出dataout

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
    reg [2:0] cnt;
    reg [3:0] data;
    
    always@(posedge clk_b or negedge brstn)
        if(!brstn) cnt<=0;
        else if(data_en) 
            begin
                if(cnt==2) cnt<=0;
                else cnt<=cnt+1;
            end
        else cnt<=0;
    
    always@(posedge clk_a or negedge arstn)
        if(!arstn) data<=0;
    else if(cnt==2 && data_en) 
            begin
               data<=data_in;
            end
        else data<=data;
    
        always@(posedge clk_b or negedge brstn)
        if(!brstn) dataout<=0;
        else dataout<=data;
endmodule