题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg div2, div4, div8;
// N-div clk,clk reverse when cnt = N/2-1 or N-1
reg [2:0] cnt2,cnt4,cnt8;

always @(posedge clk_in or negedge rst) begin
    if (!rst) cnt2 <= 'b0;
    else if(cnt2 == 3'd1) cnt2 <= 'b0;
    else cnt2 <= cnt2 + 1'd1; 
end

always @(posedge clk_in or negedge rst) begin
    if (!rst) cnt4 <= 'b0;
    else if(cnt4 == 3'd1) cnt4 <= 'b0;
    else cnt4 <= cnt4 + 1'd1; 
end

always @(posedge clk_in or negedge rst) begin
    if (!rst) cnt8 <= 'b0;
    else if(cnt8 == 3'd3) cnt8 <= 'b0;
    else cnt8 <= cnt8 + 1'd1; 
end

always @(posedge clk_in or negedge rst) begin
    if (!rst) div2<=0; 
    else if(cnt2 == 0 || cnt2==1) div2 <= ~div2;
end

always @(posedge clk_in or negedge rst) begin
    if (!rst) div4<=0; 
    else if(cnt4 == 3'd0) div4 <= ~div4;
end

always @(posedge clk_in or negedge rst) begin
    if (!rst) div8<=0; 
    else if(cnt8 == 3'd0) div8 <= ~div8;
end

assign clk_out2 = div2; 
assign clk_out4 = div4;                 
assign clk_out8 = div8; 
                 
                
                

//*************code***********//
endmodule