题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
input clk,
input rst_n,
input [7:0]a,
input [7:0]b,
input [7:0]c,

output [7:0]d
);
    wire [7:0] m,n;
//***比较a和b赋值给m***//    
compare compare_u1(
    .clk   (clk)   ,
    .rst_n (rst_n)   ,
    .x     (a)   ,
    .y     (b)  ,
 
    .z     (m)
);
//***比较a和c赋值给n***//
compare compare_u2(
    .clk   (clk)   ,
    .rst_n (rst_n)   ,
    .x     (a)   ,
    .y     (c)  ,
 
    .z     (n)
);
//***比较m和n赋值给d***//    
compare compare_u3(
    .clk   (clk)   ,
    .rst_n (rst_n)   ,
     .x     (m)   ,
     .y     (n)  ,
 
     .z     (d)
);
endmodule

module compare(
    input clk,
    input rst_n,
    input [7:0] x,
    input [7:0] y,
    
    output reg [7:0] z
);
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            z <= 8'd0;
        else if(x>y)
            z <= y;
        else 
            z <= x;

endmodule