题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module child_mod(
input            clk,
input            rst_n,
input [7:0]      data_a,
input [7:0]      data_b,
output [7:0]     c
);

reg [7:0]     c_reg;


always@ (posedge clk&nbs***bsp;negedge rst_n) begin
    if(~rst_n) begin
    c_reg <= 0; end
    else begin
       if(data_a > data_b) c_reg <= data_b;
       else c_reg <= data_a;
    end
end

assign c = c_reg;

endmodule



module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire[7:0] middle1;
wire[7:0] middle2;

child_mod   U1(
            .clk(clk),
            .rst_n(rst_n),
            .data_a(a),
            .data_b(b),
            .c(middle1)
);

child_mod   U2(
            .clk(clk),
            .rst_n(rst_n),
            .data_a(a),
            .data_b(c),
            .c(middle2)
);

child_mod   U3(
            .clk(clk),
            .rst_n(rst_n),
            .data_a(middle1),
            .data_b(middle2),
            .c(d)
);


endmodule